1. Field of the Invention
The present invention relates to a method for programming a flash memory. In particular, the present invention discloses a method of programming a flash memory through boosting a voltage level of a source line.
2. Description of the Prior Art
Recently, the demand on portable electronic devices grows dramatically. Therefore, advanced technology associated with the flash memory or the electrically erasable programmable read-only memory (EEPROM) is developed, and the corresponding market is prosperous. The portable electronic devices include films of digital cameras and storage devices of cellular phones, video game apparatuses, and personal digital assistants, answering machines, and programmable ICs. The flash memory is a non-volatile memory, and it records data through altering a threshold voltage of a transistor (a memory cell) to control establishment of the conductive channel. In addition, the stored data are not flushed when the electric power inputted into the flash memory is cut. Generally speaking, the flash memory is cataloged into an NOR cell type and an NAND cell type. It is well-known that the NOR flash memory has quick data access, and commonly functions as a code flash device for processing program codes. In addition, the NAND flash memory has a greater cell density, and commonly functions as a data flash device for storing massive data.
Please refer to FIG. 1, which is a section view of a prior art NAND flash memory 10. The flash memory 10 has an N-doped substrate 11, a deep P-well (DPW) 12, a cell N-well (CNW) 14, a shallow P-well (SPW) 16 isolated by a shallow trench isolation (STI) 15, and an NAND memory cell string 18. The NAND memory cell string 18 has a plurality of NMOS memory cells cascaded in series. In other words, the NAND memory cell string 18 shown in FIG. 1 has 8 cell transistors M0-M7 functioning as the NMOS memory cells. Each of the cell transistors M0-M7 has a stacked gate structure. The stacked gate structure has a control gate 20 and a floating gate 22. The word lines WL0-WL7 are respectively connected to control gates 20 of the cell transistors M0-M7. That is, one control gate 20 corresponds to a specific word line for receiving a word line voltage. One side of the NAND memory cell string 18 is connected to a source line selecting transistor SGS. The source line selecting transistor SGS has a structure identical to that of the cell transistor M0-M7. Therefore, the source line selecting transistor SGS also has a control gate and a floating gate. However, the control gate and the floating gate of the source line selecting transistor SGS are electrically connected. One end of the source line selecting transistor SGS is electrically connected to a source of the cell transistor M7 within the memory cell string 18, and another end of the source line selecting transistor SGS is electrically connected to the cell N-well 14. The cell N-well 14 is used for delivering a source line voltage, and functions as a source line (SL). The source line selecting transistor SGS is used to control if the cell transistor M7 is electrically connected to the source line SL. At another side of the NAND memory cell string 18, a contact plug 24 is electrically connected to a drain of the cell transistor M0, and contacts the shallow P-well 16. In other words, the drain of cell transistor M0 is electrically connected to the shallow P-well 16. In addition, the contact plug 24 also contacts a local bit line (LBL) 26, and the local bit line 26 is electrically connected to one end of a main bit line selecting transistor SGB through another contact plug 28. The main bit line selecting transistor SGB is formed on a P-well 32, and functions as a switch used for controlling if a driving voltage delivered via a main bit line (MBL) 30 is passed to the local bit line 26.
Please note that only one memory cell string 18 is shown in FIG. 1. However, as shown in FIG. 1, another source line selecting transistor, which is electrically connected to the cell N-well 14, is positioned near one side of the source line selecting transistor SGS. This source line selecting transistor is also used for controlling if cell transistors of another memory cell string (not shown) are electrically connected to the source line. Concerning the same local bit line 26, it can be connected to a plurality of memory cell strings 18. For example, the same local bit line 26 is capable of delivering one bit line voltage to 8 memory cell strings 18 for control operations of the cell transistors within 8 memory cell strings 18.
Please refer to FIG. 2, which is a first equivalent circuit diagram of the flash memory 10 shown in FIG. 1. Please note that only 8 cell transistors M0-M7 within one memory cell string 18 are shown in FIG. 1 for simplicity. However, the flash memory 10 actually is capable of having a plurality of memory cell strings 18, and each memory cell string 18 can be built by a plurality of cell transistors. The cell transistors respectively correspond to different bit lines and word lines. In FIG. 2, the flash memory 10 has two memory cell strings 34a, 34b, and each of the memory cell strings 34a, 34b has 8 cell transistors M0-M7. The memory cell string 34a corresponds to a local bit line LBL0 and a main bit line MBL0. A shallow P-well SPW is used to function as a buried bit line electrically connected to the local bit line LBL0. In addition, a P-N junction between the shallow P-well SPW0 and the cell N-well CNW can be regarded as a diode 36a. Similarly, another P-N junction between the deep P-well DPW and the cell N-well CNW functions as a diode 36b as well.
Concerning another memory cell string 34b, it corresponds to the local bit line LBL1 and the main bit line MBL1. A shallow P-well SPW1 is used to be a buried bit line electrically connected to the local bit line LBL1. In other words, both of the memory cell strings 34a, 34b have the same structure. However, the operation of the memory cell string 34a is controlled by the local bit line LBL0 and the main bit line MBL0, and the operation of the memory cell string 34b is controlled by the local bit line LBL1 and the main bit line MBL1.
With the help of the main bit line selecting transistors SGB0, SGB1 that control signals transmitted via the main bit lines MBL0, MBL1 and the source line selecting transistors SGS0, SGS1 that control signals transmitted via the source line SL, the prior art flash memory 10, as shown in FIG. 2, utilizes the buried bit lines established by the shallow P-wells SPW0, SPW1 to activate Fowler-Nordheim (FN) tunneling through low driving voltages. For example, suppose that the cell transistor M3 within the memory cell string 34b is selected, and needs to be programmed for keeping data. Now, the deep P-well DPW corresponds to a voltage level equaling 0V, and the word line WL3 corresponding to the selected cell transistor M3 is driven by a word line voltage equaling 10V. Regarding the unselected word lines WL0-WL2, WL4-WL7, they are driven by a word line voltage equaling 0V. In addition, the main bit line MBL1 corresponding to the selected cell transistor M3 is driven by a bit line voltage equaling +7V, and the unselected main bit line MBL0 is driven by a bit line voltage equaling 0V.
After the voltage level of the main bit line MBL1 is driven by a charge pump circuit to approach +7V, a driving voltage equaling +9V is inputted to the gates of the bit line selecting transistors SGB0, SGB1, and another driving voltage equaling 2V is inputted to the gates of the source line selecting transistors SGS0, SGS1. Then, the bit line selecting transistors SGB0, SGB1 are turned on. Therefore, the main bit line MBL starts driving voltage levels of the local bit line LBL0 and the buried bit line built by the shallow P-well SPW0 to approach 0V. In addition, the main bit line MBL1 starts driving voltage levels of the local bit line LBL and the buried bit line built by the shallow P-well SPW1 to approach +7V. Because the source line selecting transistors SGS0, SGS1 are not turned on, one side of each memory cell string 34a, 34b is floating. Based on the above-mentioned conditions, the selected cell transistor M3 within the memory cell string 34b expels electrons from its floating gate through the FN tunneling mechanism. The selected cell transistor M3 is adjusted to have a lower threshold voltage, and the selected cell transistor M3 is successfully programmed to record a predetermined logic value.
Generally speaking, the prior art flash memory 10 needs 200μ s to complete the above-mentioned programming operation, wherein 10μ s is required by the charge pump circuit to drive the voltage level of the main bit line MBL to approach +7V. Suppose that one memory block contains 4 k main bit lines, and each main bit line has a capacitance value equaling 6 pF. Therefore, when all of the cell transistors at the same bit line are going to be programmed, the charge pump circuit has to simultaneously drive voltage levels of the 4 k main bit lines to approach +7V. According to the well-known formula Q=C*V, that is, 7V*4 k*6 pF=10μ s*l, it is obvious that the required maximum driving current I corresponds to 16.8 mA. Because the main bit line has a greater capacitance value, the charge pump circuit needs to have a great driving capacity for driving the voltage levels of the main bit lines to approach +7V in 10μ s. In other words, the charge pump circuit requires a larger chip area to accommodate desired circuit components used for generating the needed driving current. Therefore, it is difficult to reduce the overall size of the flash memory 10 owing to the implemented charge pump circuit.